A Low Power Memory Design Using Clock Gating Technique
نویسنده
چکیده
Along with the progress of VLSI technology delay buffers plays an increasingly critical role on affecting the circuit design and performance. This paper presents the design of a low power buffer. A gated clock ring counter is used to access the memory. The ring counter uses Double edge triggered flip flops instead of traditional flip flops to half the operating frequency. Also combinational elements are used in the control logic for generating the clock gating signals to
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